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CXA1734S
US Audio Multiplexing Decoder For the availability of this product, please contact the sales office.
Description The CXA1734S is an IC designed as a decoder for the Zenith TV Multi-channel System also corresponds with I2C BUS. Functions include stereo demodulation, SAP (Separate Audio Program) demodulation and dbx noise reduction. Various kinds of filters are built in while adjustment and mode control are all executed through I2C BUS. Features * Audio multiplexing decoder and dbx noise reduction decoder are all included in a single chip. Almost any sort of signal processing is possible through this IC. * All adjustments are possible through I2C BUS to allow for automatic adjustment. * Various built-in filter circuits greatly reduce external parts. Standard I/O Level * Input level COMPIN (Pin 11) 245 mVrms * Output level LOUT (Pin 29) 490 mVrms ROUT (Pin 28) 490 mVrms 30 pin SDIP (Plastic)
Absolute Maximum Ratings (Ta=25C) 11 * Supply voltage VCC * Operating temperature Topr -20 to +75 * Storage temperature Tstg -65 to +150 * Allowable power dissipation PD 1.35 Range of Operating Supply Voltage 9 0.5
V C C W V
Applications TV, VCR and other decoding systems for US audio multiplexing TV broadcasting Structure Bipolar silicon monolithic IC
Pin Configuration (Top View)
VCAWGT NOISETC VEWGT SAPOUT
VCATC
VEOUT
ROUT
VCAIN
ITIME
LOUT
VETC
SAPIN
30
29
28
27
26
25
24
23
22
21
20
19
18
17
GND
NC
VE
16
1
SDA
2
SCL
3
DGND
4
SAD
5
VGR
6
IREF
7
MAININ
8
MAINOUT
9
PLINT
10
STFIL
11
COMPIN
12
SAPTC
13
SUBOUT
14
STIN
15
VCC
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
--1--
E94612B5Z-TE
SUBOUT
PLINT
MAINOUT
STFIL
10
9
13
8
Block Diagram
STLPF
"STLPF" VCO 1/4 1/2 29 MATRIX FLT LPF VCA 28 LOUT ROUT
LFLT
"STEREO" WIDEBAND DeEm LPF +6dB STIND SAPVDET "SAPVCO" LOGIC NRSW/FOMO/SAPC/M1
COMPIN
11
VCA
LPF
VCC
15
ATT
SCL
VGR
SAD
SDA
IREF
STIN
VE
DGND
SAPIN
VETC
VCAIN
SAPOUT
VEWGT
VEOUT
VCAWGT
VCATC
--2--
SAPVCO
GND LPF DeEm NOISE DET "NOISE" "SAP" SAPIND HPF
17
BPF
MAININ
7
VE
VCA
NOISETC 16
RMSDET
SAPTC "SAPLPF"
12
STLPF STVCO SAPLPF SAPVCO
SPECTRAL LPF LPF RMSDET
SAPFDET I2 C BUS I/F
AMP (+4dB)
ITIME "PONRES"
27
IRE F
SW
5
6
4
3
2
1
18
19
14
20
21
22
23
24
25
26
CXA1734S
CXA1734S
Pin Description Pin No. Symbol Pin voltage Equivalent circuit
VCC 7.5k 35 2.1V x2 4k x5
(Ta = 25C, VCC = 9 V) Description
1
SDA
--
7.5k
4.5k
3k
Serial data I/O pin. VIH > 3.0 V VIL < 1.5 V
1
VCC 7.5k 35 2.1V 4k
2
SCL
--
19.5k x4 3k
Serial clock input pin. VIH > 3.0 V VIL < 1.5 V
2
3
DGND
--
3
Digital block GND.
VCC 40k 80k
2V
4
4
SAD
--
10k
Slave address control switch. The slave address is selected by changing the voltage applied to this pin.
3k
147
5
VGR
1.3V
11k
9.7k
19.4k x4 2.06k
VCC 11k 11k
Band gap reference output pin. Connect a 10 F capacitor between this pin and GND.
5
1.3V
--3--
CXA1734S
Pin No.
Symbol
Pin voltage
40k
Equivalent circuit
Description
40k
30k
30k
15k x2
30k
VCC
6
IREF
1.3V
30p 1.8k
6
147 6.3k
Set the filter and VCO reference current. The reference current is adjusted with the BUS DATA based on the current which flows to this pin. (Connect a 62 k 1%) resistor between this pin and GND.)
16k
VCC 23k 23k 10
VCC
7
MAININ
4.0V
147
Input the (L + R) signal from MAINOUT (Pin 8).
7
47k 4V VCC 15k x4 VCC 147
8
MAINOUT
4.0V
8
(L + R) signal output pin.
200
1k
VCC 12k 12k
147
9
PLINT
6.3V
20k 20k
9
Pilot cancel circuit loop filter integrating pin. (Connect a 1 F capacitor between this pin and GND.)
26
20k 50
10k
--4--
CXA1734S
Pin No.
Symbol
Pin voltage
Equivalent circuit
VCC 3k 3k
Description
150k
10
STFIL
5.3V
75k 75k
4k
4k 147
10
Stereo block PLL loop filter integrating pin.
12k
1k
1k VCC
50k 147 11
11
COMPIN
4.0V
22k
20k 3V 3k
Audio multiplexing signal input pin.
4k
4k
4k
16k
24k
VCC 8k 10 k 3k
1k
12
SAPTC
4.5V
VCC 4k 12 50
Set the time constant for the SAP carrier detection circuit. (Connect a 4.7 F capacitor between this pin and GND.)
Vcc 2k 2k 10P 4k
13
SUBOUT
4.0V
14.4k 2k 2k
500 500 147 13
(L - R) signal output pin.
2k
4k
1k
--5--
CXA1734S
Pin No.
Symbol
Pin voltage
Equivalent circuit
23k
Description
23k
14
STIN
4.0V
11.7k 147 14 147 19 47k 4V 20k 15 Vcc 8k 3.3k 4V 47k
Input the (L - R) signal from SUBOUT (Pin 13).
19
SAPIN
4.0V
Input the (SAP) signal from SAPOUT (Pin 18).
15
VCC
--
Supply voltage pin.
Set the time constant for
10k 1k 2k 4k 4V 3k
16
NOISETC
3.0V
x2 3k Vcc
the noise detection circuit. (Connect a 4.7 F capacitor and a 200 k resistor between this pin and GND.)
16
17
GND
--
17
Analog block GND.
Vcc 5P
500
18
SAPOUT
4.0V
500
7.4k 147 17k 18
SAP FM detector output pin.
24k 10
4k 50 4V
7.5k
20
VE
4.0V
20
147
Variable de-emphasis integrating pin. (Connect a 2700 pF capacitor and a 3.3 k resistor in series between this pin and GND.)
--6--
CXA1734S
Pin No.
Symbol
Pin voltage
Equivalent circuit
Vcc
Description
500
2.9V 4V 36k
21
VEWGT
4.0V
21 147 500
Weight the variable deemphasis control effective value detection circuit. (Connect a 0.047 F capacitor and a 3 k resistor in series between this pin and GND.)
8k
30k 8
4k 50 Vcc
22
VETC
1.7V
x4
22 x4
20k 50 4V 7.5
Determine the restoration time constant of the variable de-emphasis control effective value detection circuit. The specified restoration time constant can be obtained by connecting a 3.3 F capacitor between this pin and GND.
Vcc 5P
500
23
VEOUT
4.0V
23 10k 500
Variable de-emphasis output pin. (Connect a 4.7 F nonpolar capacitor between Pins 23 and 24.)
VCC
47k
47k
24
VCAIN
4.0V
20k
VCC
24
VCA input pin. Input the variable deemphasis output signal from Pin 23 via a coupling capacitor.
--7--
CXA1734S
Pin No.
Symbol
Pin voltage
40k
Equivalent circuit
VCC 40k 3p
Description
500
25
VCAWGT
4.0V
25 2.9V 36k 500 147
50
4k
8
30k
8k
Weight the VCA control effective value detection circuit. (Connect a 1 F capacitor and a 3.9 k resistor in series between this pin and GND.)
VCC
x4
26 x4
26
VCATC
1.7V
50
4k
7.5
20k
Determine the restoration time constant of the VCA control effective value detection circuit. The specified restoration time constant can be obtained by connecting a 10 F capacitor between this pin and GND. Set the reference current for the effective value detection timing current. The reference current is adjusted with the BUS DATA "SPECTRAL" based on the current which flows to this pin. The timing current determines the restoration time constant of the detection circuit and the variable de-emphasis characteristics. Connect a 43 k (1%) resistor between this pin and GND.
VCC 40k 40k 30k 20k 40k 10k
2.6V
27
ITIME
1.3V
30p 1.8k 47k 25k x4 27 147
--8--
CXA1734S
Pin No.
Symbol
Pin voltage
Equivalent circuit
VCC 3k
Description
28
ROUT
500 15k
Right channel output pin.
4.0V 29 LOUT
28 29 500 3p
Left channel output pin.
30
NC
--
30
--
--9--
Electrical Characteristics =245mVrms =490mVrms =49mVrms =147mVrms (Pre-Emphasis : OFF) (dbx-TV : OFF)
COMPIN input level (100% modulation level)
Main (L+R) SUB (L-R) Pilot SAP Carrier
fH=15.734kHz Min. 22 Using 15 kHz LPF 440 -1.2 -3.0 Using 15 kHz LPF Using 15 kHz LPF Using 15 kHz LPF
Compared with the TEST2 output level
No. Mode Input Input signal Others 32 490 0 -1.0 -- -- 61 150 -3.0 Using 15 kHz LPF Using 15 kHz LPF 13 13 13 fH fH -- -- Using 15 kHz LPF
Compared with the TEST8 output level
Item Typ. -- -- Mono 11 11 11 11 11 11 NO Signal 13 13 13 11 11 11 11 11 11 11 11 Mono Mono Mono Mono Mono ST ST ST ST ST ST ST ST
Symbol
Conditions Output
Max. 42 540 1.0
Unit mA mVrms
1
Current consumption
Icc
2
Main output level
Vmain
3
FCdeem
dB 1.0 0.1 0.15 69 190 Using 15 kHz LPF -0.5 -- -- 56 Using fH BPF 0dB=49mVrms 0dB=49mVrms -- -8.0 3.5 0.1 0.5 64 1.0 -6.0 6.0 0.5 % 0.5 -- 230 1.0 1.0 % 2.0 -- 7.0 -4.0 dB 8.5
CXA1734S
4
De-emphasis frequency characteristics Main LPF frequency characteristics
FCmain
5
Main distortion
THDm
--10-- SUB 1k 100% NR-OFF SUB 12k 30% NR-OFF SUB 1k 100% NR-OFF SUB 1k 200% NR-OFF fH 0dB (49mVrms) fH 0dB (49mVrms)
6
Main overload distortion
THDmmax
MAIN 1k 100% Pre-em ON MAIN 5k 30% Pre-em ON MAIN 12k 30% Pre-em ON MAIN 1k 100% Pre-em ON MAIN 1k 200% Pre-em ON 28 29 28 29 28 29 28 29 28 29 28 29
7
Mono S/N
SNmain
dB mVrms dB
8
Sub output level
Vsub
9
Sub LPF frequency characteristics
FCsub
10
Sub distortion
THDsub
11
Sub overload distortion
THDsmax
12
Sub S/N
SNsub
dB mVrms
13
Sub pilot leak
PCsub
14
ST on level
THst
15
ST on/off hysteresis
HYst
No. Mode Input 11 23 35 dB 23 35 190 0 2.5 56 -12 2.5 -9 4 230 2.5 6.0 -- 46 -6.5 5.5 dB 150 -3.0 Using 15kHz LPF Using 15kHz LPF
Compared with the TEST18 output level
Item Min. Typ. -- -- mVrms dB % Unit Max. ST ST 11 11 18 18 18 18 -- -- 0dB=147mVrms 0dB=147mVrms -- Using 15kHz LPF 11 11 11 11 SAP Carrier SAP Carrier 11 SAP SAP SAP SAP SAP SAP
Symbol
16
ST separation 1
STsep1
17
ST separation 2
STsep2
Conditions Output 28 29 28 29 Others LR RL LR RL
18
SAP output level
Vsap
19
SAP LPF frequency characteristics
FCsap
20
SAP distortion
THDsap
21
SAP S/N
SNsap
Input signal ST 300Hz 30%, NR-ON ST 3kHz 30%, NR-ON SAP 1k 100% NR-OFF SAP 10k 30% NR-OFF SAP 1k 100% NR-OFF SAP Carrier 147mVrms
22
SAP on level
THsap
23
SAP on/off hysteresis
HYsap
--11--
CXA1734S
CXA1734S
I2C BUS block items (SDA, SCL) No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Item High level input voltage Low level input voltage High level input current Low level input current Low level output voltage SDA (Pin 1) during 3 mA inflow Max. inflow current Input capacitance Max. clock frequency Minimum waiting time for data change Minimum waiting time for start of data transfer Low level clock pulse width High level clock pulse width Minimum waiting time for start preparation Min. data hold time Min. data preparation time Rise time Fall time Minimum waiting time for stop preparation Symbol VIH VIL IIH IIL VOL IOL CI fSCL tBUF tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tR tF tSU:STO Min. 3.0 0 -- -- 0 3 -- 0 4.7 4.0 4.7 4.0 4.7 0 250 -- -- 4.7 Typ. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max. 5.0 1.5 10 10 0.4 -- 10 100 -- -- -- -- -- -- -- 1 300 -- Unit V A V mA pF kHz
s
ns s ns s
I2C BUS load conditions:
Pull-up resistor 4 k (Connect to +5 V) Load capacity 200 pF (Connect to GND)
I2C BUS Control Signal
SDA
tBUF SCL
tR
tF
tHD;STA
P
S
tHD;STA
tLOW
tHD;DAT
tHIGH
tSU;STA tSU;DAT Sr
tSU;STO P
--12--
R1
30
SDA
220 R2 4.7
29
I2C BUS DATA
SCL
220
28
DGND
27
Electrical Characteristics Measurement Circuit
DGND
C3 10 R4 62k METAL 1%
SAD
26
VGR
25
IREF
24
MAININ
FILTERS
15kHz LPF fHBPF
23
MAINOUT
C8
22
C10 0.47
1 R6 2.2k C11 0.22 C13
PLINT
MEASURES
21
STFIL
20
COMPIN
4.7 C18 4.7
19
SIGNAL GENERATOR
SAPTC
18
SUBOUT
17
STIN
16
VCC
C19
VCC
100
--13--
1 2 3 4 5 6 7
C6
NC
LOUT
C1 4.7
ROUT
C2 R3 43k METAL 1% 10
ITIME
S2
S3
S4
S1
VCATC
C4 TANTALUM 1 R5
VCAWGT
BUFF
C5
3.9k
VCAIN
C7
4.7
4.7
8 9
10 11
VEOUT
TANTALUM 3.3
VETC
C9 0.047 C12 2700p R7 3k R8 3.3k
VEWGT
VE
C14
V2
AC
GND
CXA1734S
12 13
SAPIN
C15
4.7
SAPOUT
C17
4.7
14 15
GND
4.7
NOISETC
C16 R9 200k
A
9V
V1
GND
CXA1734S
I2C BUS Register Data Standard Setting Values Register ATT STVCO SAPVCO SAPLPF STLPF SPECTRAL WIDEBAND TEST-DA TEST1 NRSW FOMO M1 SAPC ATTSW Number of Classification bits 4 A 6 A 4 A 4 A 6 A 6 A 6 A 1 T 1 T 1 U 1 U 1 U 1 S 1 S Standard setting 9 1F 8 8 1F 1F 1F 0 0 -- -- 1 -- -- Contents Setting value when electrical characteristics are measured
Center point
Adjustment point
Normal mode According to the mode control table Mute OFF Fixed by the set specifications
Classification
A: U: S: T:
Adjustment User control Proper to set Test
List of Adjustment Contents
Adjustment item 1 MAIN VCA 2 ST VCO ATT STVCO Adjustment data Input pin COMPIN (Pin 11) None Input signal 100Hz 245mVrms None 5fH (78.67k) 147mVrms 9.4kHz 600mVrms 88kHz 120mVrms ST-L 30% 300Hz ST-L 30% 3kHz Measurement item level frequency STA7 (SAPVCO1) STA8 (SAPVCO2) STA3 (STLPF) STA4 (SAPLPF) ROUT output level ROUT output level Adjustment contents Test mode setting
LOUT output Adjust as close to 490 mVrms as possible kHz as possible Adjust to the center of the SAPVCO1 = 0, SAPVCO2 = 1 condition Adjust to the center of the STLPF = 1 condition Adjust to the center of the SAPLPF = 1 condition Minimize the output level Minimize the output level TEST1=1 TEST1=1 TEST-DA=1 ROUT output Adjust as close to 62.936
3 SAP VCO
SAPVCO
COMPIN (Pin 11) COMPIN (Pin 11) COMPIN (Pin 11) COMPIN (Pin 11) COMPIN (Pin 11)
4 5
ST & dbx FILTER SAP FILTER Low frequency ST separation High frequency ST separation
STLPF SAPLPF WIDEBAND SPECTRAL
6
--14--
CXA1734S
Adjustment Method 1 ATT adjustment 1. TEST BIT is set to "TEST1 = 0" and "TEST-DA = 0". 2. Input a 100 Hz, 245 mVrms sine wave signal to COMPIN and monitor the LOUT output level. Then, adjust the "ATT" data for ATT adjustment so that LOUT output goes to the standard value. 3. Adjustment range: 30% Adjustment bits: 4 bits 2 Stereo VCO adjustment 1. TEST BIT is set to "TEST1 = 0" and "TEST-DA = 1". 2. Monitor the ROUT output (4 fH free run) frequency in a no input state, and adjust "STVCO" adjustment data so that this frequency is as close to 4fH (62.936 kHz) as possible. 3. Adjustment range: 20% Adjustment bits: 6 bits SAPVCO adjustment 1. TEST BIT is set to "TEST1 = 0" and "TEST-DA = 0". 2. Input a 5fH (SAP carrier , 78.67 kHz) , 147 mVrms sine wave signal to COMPIN. While monitoring the STATUS FLAG (STA7, STA8) condition, adjust "SAPVCO" adjustment data. 3. Adjustment range: 20% Adjustment bits: 4 bits Align SAPVCO with the center of the STA7 = 0 and STA8 = 1 (adjustment OK) condition range.
Adjustment point Control data "SAPVCO"
3
0 1 0 1 0
F
Measurement data STA7 "SAPVCO1" STA8 "SAPVCO2"
4
Stereo block dbx filter adjustment 1. TEST BIT is set to "TEST1 = 1" and "TEST-DA = 0". 2. Input a 9.4 kHz, 600 mVrms sine wave signal to COMPIN. While monitoring the STATUS FLAG (STA3) condition, adjust the "STLPF" adjustment data. 3. Adjustment range: 20% Adjustment bits: 6 bits Align STLPF with the center of the STA3 = 1 (adjustment OK) condition range.
Adjustment point Control data "STLPF"
0 1 0
3F
Measurement data STA3 "STLPF"
--15--
CXA1734S
5
SAP block filter adjustment 1. TEST BIT is set to "TEST1 = 1" and "TEST-DA = 0". 2. Input a 88 kHz, 120 mVrms sine wave signal to COMPIN. While monitoring the STATUS FLAG (STA4) condition, vary and adjust the "SAPLPF" adjustment data. 3. Adjustment range: 20% Adjustment bits: 4 bits Align SAPLPF with the center of the STA4 = 1 (adjustment OK) condition range.
Adjustment point Control data "SAPLPF"
0 1 0
F
Measurement data STA4 "SAPLPF"
6
Separation adjustment 1. TEST BIT is set to "TEST1 = 0" and "TEST-DA = 0". 2. Set the unit to stereo mode and input the left channel only signal (modulation factor 30%, frequency 300 Hz) to COMPIN. At this time, adjust the "WIDEBAND" adjustment data to reduce ROUT output to the minimum. 3. Next, set the frequency only of the input signal to 3 kHz and adjust the "SPECTRAL" adjustment data to reduce ROUT output to the minimum. 4. Then, the adjustments in 2 and 3 above are performed to optimize the separation. 5. "WIDEBAND" "SPECTRAL" Adjustment range: 30% Adjustment range: 15% Adjustment bits: 6 bits Adjustment bits: 6 bits
--16--
CXA1734S
Description of Operation The US audio multiplexing system possesses the base band spectrum shown in Fig. 1.
PEAK DEV kHz 50 AM-DSB-SC 50
25
25
L-R dbx-TV NR
PILOT
L+R 50-15kHz
5 fH 2fH 3fH 4fH
SAP dbx-TV NR FM 10kHz 50-10kHz 5fH
15 TELEMETRY FM 3kHz 3 6fH 6.5fH f
fH=15.734kHz
Fig. 1. Base band spectrum
2fHL0 PLL (VCO 8fH) STEREO LPF MVCA PILOT CANCEL SUB LPF L-R (DSB) DET SAP(FM) SAP BPF DET INJ. LOCK NOISE DET SAP LPF (SAP OUT) WIDEBAND SUBVCA fHL90 fHL0 PILOT DET MAIN LPF DE.EM I2C BUS DECODER MODE CONTROL (MAIN OUT) (MAIN IN)
(COMPIN)
11
8
L+R 4.7
7
(SUBOUT) (ST IN)
MATRIX
13
4.7 L-R
14
NR SW
(L-OUT)
29
A
dbx-TV BLOCK
B
(R-OUT)
28
18
(SAP IN) I2C BUS 4.7 DECODER
19
MODE CONTROL
SAP DET
I2C BUS DECODER MODE CONTROL
Fig. 2. Overall block diagram (See Fig. 3 for the dbx-TV block)
FIXED
VARIABLE
14
NR SW
A
DEEMPHASIS DEEMPHASIS (VE OUT) (VCA IN)
B
VCA TO MATRIX
23 19
HPF LPF LPF 4.7
24
RMS DET RMS DET
Fig. 3. dbx-TV block --17--
CXA1734S
(1) L + R (MAIN) After the audio multiplexing signal input from COMPIN (Pin 11) passes through MVCA, the SAP signal and telemetry signal are suppressed by STEREO LPF. Next, the pilot signals are canceled. Finally, the L - R signal and SAP signal are removed by MAIN LPF, and frequency characteristics are flattened (de-emphasized) and input to the matrix. (2) L - R (SUB) The L - R signal follows the same course as L + R before the pilot signal is canceled. L - R has no carrier signal, as it is a suppressed-carrier double-sideband amplitude modulated signal (DSB-AM modulated). For this reason, the pilot signal is used to regenerate the carrier signal (quasi-sine wave) to be used for the demodulation of the L - R signal. In the last stage, the residual high frequency components are removed by SUB LPF and the L - R signal is input to the dbx-TV block via the NRSW circuit after passing through SUBVCA. (3) SAP SAP is an FM signal using 5fH as a carrier as shown in the Fig.1. First, the SAP signal only is extracted using SAP BPF. Then, this is subjected to FM detection. Finally, residual high frequency components are removed and freqency characteristics flattened using SAP LPF, and the SAP signal is input to the dbx-TV block via the NRSW circuit. When there is no SAP signal, the Pin 18 output is soft muted. (4) Mode discrimination Stereo discrimination is performed by detecting the pilot signal amplitude. SAP discrimination is performed by detecting the 5fH carrier amplitude. NOISE discrimination is performed by detecting the noise near 25 kHz after FM detection. (5) dbx-TV block Either the SAP signal or L - R signal input respectively from ST IN (Pin 14) or SAP IN (Pin 19) is selected by the mode control and input to the dbx-TV block. The input signal then passes through the fixed de-emphasis circuit and is applied to the variable deemphasis circuit. The signal output from the variable de-emphasis circuit passes through an external capacitor and is applied to VCA (voltage control amplifier). Finally, the VCA output is converted from a current to a voltage using an operational amplifier and then input to the matrix. The variable de-emphasis circuit transmittance and VCA gain are respectively controlled by each of effective value detection circuits. Each of the effective value detection circuits passes the input signal through a predetermined filter for weighting before the effective value of the weighted signal is detected to provide the control signal. (6) Others "MVCA" is a VCA which adjusts the input signal level to the standard level of this IC. In addition, the input signal enters the decoder without passing through MVCA by setting to ATTSW = 1. The signals (L + R, L - R, SAP) input to "MATRIX" are selected according to the BUS data and whether there is ST or SAP discrimination, and any one of the ST-L, ST-R, MONO or SAP signals is output to LOUT and ROUT. "Bias" supplies the reference voltage and reference current to the other blocks. The currents flowing to the resistors connecting IREF (Pin 6) and ITIME (Pin 27) with GND become the reference current.
--18--
CXA1734S
Register Specifications Slave address SAD pin GND VCC SLAVE RECEIVER 80H 8AH SLAVE TRANSMITTER 81H 8BH
Register table SUB ADDRESS MSB LSB 0000 0001 0010 0011 0100 0101 0110 DATA BIT7 BIT6 ATTSW BIT5 TEST-DA BIT4 BIT3 BIT2 BIT1 BIT0 TEST1 ATT [4] INPUT LEVEL adj STVCO [6] STEREO VCO adj (SAPLPF [4] SAP FILTER adj) STLPF [6] ST FILTER adj SPECTRAL [6] WIDEBAND [6] NRSW FOMO SAPC M1 : Don't Care Status Register When TEST1 = 0 STA1 BIT7 POWER ON RESET STA2 BIT6 STEREO STA3 BIT5 SAP STA4 BIT4 NOISE STA5 BIT3 -- STA6 BIT2 -- STA7 BIT1 SAP VCO1 STA8 BIT0 SAP VCO2
(SAPVCO [4] SAP VCO adj)
When TEST1 = 1 STA1 BIT7 POWER ON RESET STA2 BIT6 STEREO STA3 BIT5 STLPF STA4 BIT4 SAPLPF STA5 BIT3 -- STA6 BIT2 -- STA7 BIT1 -- STA8 BIT0 --
--19--
CXA1734S
Description of Registers Control registers Register ATT STVCO SAPVCO SAPLPF STLPF SPECTRAL WIDEBAND TEST-DA TEST1 NRSW FOMO M1 SAPC ATTSW Classification Number of bits 4 6 4 4 6 6 6 1 1 1 1 1 1 1 U: A: S: T: Classification A A A A A A A T T U U U S S User control Adjustment Proper to set Test Contents Input level adjustment STEREO VCO free running frequency adjustment SAP VCO free running frequency adjustment SAP filter adjustment STEREO and dbx filter adjustment Adjustment of stereo separation (3 kHz) Adjustment of stereo separation (300 Hz) Turn to DAC test mode and STVCO adjustment mode by means of TEST-DA = 1. Turn to test mode by means of TEST = 1. (Adjustment of STLPF and SAPLPF) Selection of the output signal (STEREO mode , SAP mode) Turn to forced MONO by means of FOMO = 1. (LOUT only is MONO during SAP output.) Selection of mute ON/OFF (0: mute ON, 1: mute OFF) Selection of SAP mode or L + R mode according to the presence of SAP broadcasting Turns the input stage MVCA off when ATTSW = 1.
Status registers Register PONRES STEREO SAP NOISE STLPF SAPLPF SAPVCO1 SAPVCO2 Number of bits 1 1 1 1 1 1 1 1 Contents POWER ON RESET detection; 1: RESET Stereo discrimination of the input signal; 1: Stereo SAP discrimination of the input signal; 1: SAP Noise level discrimination of the input signal mode; 1: Noise Status of STEREO filter adjustment; 1: OK range Status of SAP filter adjustment; 1: OK range Status 1 of SAP VCO free running frequency adjustment; 0: OK range Status 2 of SAP VCO free running frequency adjustment; 1: OK range
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CXA1734S
Description of Control Registers ATT (4): Adjust the signal level input to COMPIN (Pin 11) to the reference level (245 mVrms). Variable range of the input signal: 245 mVrms -5.0 dB to +3.0 dB 0 = Level min. F = Level max. STVCO (6): Adjust STEREO VCO free running frequency (f0). Variable range: f0 20% 0 = Free running frequency min. 3F = Free running frequency max. Adjust SAPVCO free running frequency (f0). Variable range: f0 20% 0 = Free running frequency min. F = Free running frequency max. Adjust the filter f0 of the SAP block. Variable range: f0 20% 0 = Frequency min. F = Frequency max. Adjust the filter f0 of the ST and dbx blocks. Variable range: f0 20% 0 = Frequency min. 3F = Frequency max.
SAPVCO (4):
SAPLPF (4):
STLPF (6):
SPECTRAL (6): Perform high frequency (fs = 3 kHz) separation adjustment. 0 = Level max. 3F = Level min. WIDEBAND (6): Perform low frequency (fs = 300 Hz) separation adjustment. 0 = Level min. 3F = Level max. TEST1 (1): Set filter adjustment mode. 0 = Normal mode 1 = STLPF (STA3) and SAPLPF (STA4) adjustment mode In addition, the following outputs are present at Pins 28 and 29. LOUT (Pin 29): SAP BPF OUT ROUT (Pin 28): NR BPF OUT Set DAC output test mode and STVCO adjustment mode. 0 = Normal mode 1 = DAC output test mode and STVCO adjustment mode LOUT (Pin 29): DA control DC level ROUT (Pin 28): STEREO VCO oscillation frequency (4 fH)
TEST-DA (1):
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CXA1734S
NRSW (1)
Select stereo mode or SAP mode 0 = Stereo mode 1 = SAP mode Select forced MONO mode 0 = Normal mode 1 = Forced MONO mode Select the SAP signal output mode When there is no SAP signal, the conditions for selecting SAP output are selected by SAPC. 0 = L + R output is selected 1 = SAP output is selected MAIN VCA switch 0 = Normal mode 1 = MAIN VCA is passed. Mute the LOUT and ROUT output 0 = Mute ON 1 = Mute OFF
FOMO (1):
SAPC (1):
ATTSW (1)
M1 (1)
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CXA1734S
Description of Mode Control Priority ranking: TEST-DA > TEST1 > M1 > (NRSW & FOMO & SAPC) Mode control SAPC=0 "Select dbx input and LOUT & ROUT output" Conditions: FOMO = 0 NRSW = 0 (MONO or ST output) * During ST input: * During other input: NRSW LOUT : L, ROUT : R LOUT : L + R, ROUT : L + R SAPC=1 "Select dbx input and LOUT & ROUT output" Conditions: FOMO = 0 NRSW = 0 (MONO or ST output) As on the left
NRSW = 1 (SAP output) NRSW = 1 (SAP output) * Regardless of the presence of SAP * When there is "SAP" during SAP discrimination, discrimination dbx input: "SAP" LOUT: SAP, ROUT: SAP LOUT: SAP, ROUT: SAP * When there is "No SAP", output is the same However, when there is no SAP, SAPLPF as when NRSW = 0. output is soft muted (-7 dB)
FOMO
SAPC
M1
TEST1
TEST-DA
"Forced MONO" FOMO = 1 * During SAP output: LOUT: L + R, ROUT: SAP * During ST or MONO output: LOUT: L + R, ROUT: L + R Change the selection conditions for "MONO or ST output" and "SAP output". SAPC = 0: Switch to SAP output when there is SAP discrimination. Do not switch to SAP output when there is no SAP discrimination. SAPC = 1: Switch to SAP output regardless of whether there is SAP discrimination. "MUTE" M1 = 0 Output is muted. "TEST1" TEST1 = 1 Return adjustment data with STATUS REGISTER as an adjustment mode. In addition, outputs are as follows. LOUT: SAP BPF OUT ROUT: NR BPF OUT "TEST-DA" TEST-DA = 1 Used to TEST of D/A. LOUT: D/A output ROUT: STVCO oscillation frequency (4 fH)
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CXA1734S
Mode Control No. 1 (SAPC = 1) Input signal mode Mode detection ST SAP NOISE 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 1 0 1 0 1 1 1 1 1 1 1 0 0 1 0 0 1 1 1 1 0 1 0 1 0 1 0 0 1 0 0 1 1 0 1 1 1 1 1 1 1 1 0 1 1 0 1 1 1 1 1 1 Mode control NRSW FOMO SAPC 0 1 1 0 1 1 1 1 0 1 1 0 1 1 1 1 0 0 1 0 1 1 0 0 1 0 1 1 1 0 1 1 1 1 1 0 1 1 1 1 0 0 1 0 1 1 1 0 1 1 1 1 1 0 1 1 1 1 0 0 1 0 1 1 1 0 1 1 1 1 1 0 1 1 1 1 dbx input MUTE SAP SAP MUTE (SAP) (SAP) L-R MUTE L-R MUTE SAP SAP (SAP) (SAP) MUTE MUTE SAP SAP (SAP) (SAP) L-R MUTE SAP SAP (SAP) (SAP) Output Lch Rch L+R L+R SAP SAP L+R SAP L+R L+R (SAP) (SAP) L+R (SAP) L R L+R L+R L R L+R L+R SAP SAP L+R SAP (SAP) (SAP) L+R (SAP) L+R L+R L+R L+R SAP SAP L+R SAP (SAP) (SAP) L+R (SAP) L R L+R L+R SAP SAP L+R SAP (SAP) (SAP) L+R (SAP)
MONO
1)
STEREO
1)
MONO & SAP
STEREO & SAP
Note) (SAP) : The SAPOUT output signal is soft muted (approximately -7 dB). The signal is soft muted when NOISE = 1. : Don't care. 1) : SAP or NOISE discrimination may be made during MONO or STEREO input when the noise is inputted in the weak electric field. "NOISE" status rises earlier than "SAP" status when the amount of noise is increased to COMPIN.
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CXA1734S
Mode Control No. 2 (SAPC = 0) Input signal mode Mode detection ST SAP NOISE 0 0 0 1 1 0 1 1 0 1 1 0 1 1 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 0 1 0 0 1 0 0 1 0 0 1 0 0 1 1 0 1 1 0 1 1 0 1 1 1 1 0 1 1 0 1 1 0 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 Mode control NRSW FOMO SAPC 0 0 0 0 0 1 0 1 0 0 1 1 0 0 0 0 0 1 0 1 0 0 1 1 0 0 0 0 0 1 0 1 0 0 1 1 0 0 0 0 0 1 0 1 0 0 1 1 0 0 0 0 0 1 0 1 0 0 1 1 0 0 0 0 0 1 0 1 0 0 1 1 0 0 0 0 0 1 0 1 0 0 1 1 0 dbx input MUTE MUTE MUTE (SAP) (SAP) L-R MUTE L-R MUTE L-R MUTE (SAP) (SAP) MUTE MUTE SAP SAP MUTE MUTE MUTE MUTE L-R MUTE SAP SAP L-R MUTE L-R MUTE Output Lch Rch L+R L+R L+R L+R L+R L+R (SAP) (SAP) L+R (SAP) L R L+R L+R L R L+R L+R L R L+R L+R (SAP) (SAP) L+R (SAP) L+R L+R L+R L+R SAP SAP L+R SAP L+R L+R L+R L+R L+R L+R L+R L+R L R L+R L+R SAP SAP L+R SAP L R L+R L+R L R L+R L+R
MONO
1)
STEREO
1)
MONO & SAP
STEREO & SAP
Note) (SAP) : The SAPOUT output signal is soft muted (approximately -7 dB). The signal is soft muted when NOISE = 1. : Don't care. 1) : SAP or NOISE discrimination may be made during MONO or STEREO input when the noise is inputted in the weak electric field. "NOISE" status rises earlier than "SAP" status when the amount of noise is increased to COMPIN.
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CXA1734S
I2C BUS Signal There are two I2C signals, SDA (Serial DATA) and SCL (Serial CLOCK) signal. SDA is a bidirectional signal. * Accordingly there are 3 values outputs, H, L and HIZ.
H
L
HIZ
L
* I2C transfer begins with Start Condition and ends with Stop Condition.
Start Condition S SDA Stop Condition P
SCL
* I2C data Write (Write from I2C controller to the IC)
L during Write SDA MSB HIZ MSB LSB HIZ
SCL
1 S
2
3
4
5
6
7
8
9
1
8
9
Address MSB LSB HIZ HIZ
ACK
Sub Address
ACK
1
8
9
1
8
9
DATA(n)
ACK
DATA(n+1)
ACK
DATA(n+2)
HIZ
HIZ
8 DATA
9 ACK
1 DATA
8
9 P ACK
Data can be transferred in 8-bit units to be set as required. Sub address is incremented automatically.
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CXA1734S
* I2C data Read (Read from the IC to I2C controller)
H during Read SDA HIZ
SCL 1 S Address ACK DATA ACK 6 7 8 9 1 7 8 9 P
* Read timing
MSB IC output SDA
LSB
SCL
9
1
2
3
4
5
6
7
8
9
Read timing ACK DATA ACK
Data Read is performed during SCL rise.
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CXA1734S
Input level vs. Distortion characteristics 1 (MONO) Input signal: MONO (Pre-emphasis on), 1 kHz 0dB=100% modulation LPF VCC=9V, 30kHz using LPF Measurement point: L/R out
Input level vs. Distortion characteristics 2 (Stereo) Input signal: Stereo L=-R (dbx-TVNR ON), 1kHz 0dB=100% modulation level VCC=9V, 30kHz using LPF, ST mode Measurement point: L/R out
1.0
10
Distortion (%)
0.1
Distortion (%)
1.0 Standard level (100%) -10 0 Input level [dB] 10 Standard level (100%) -10 0 Input level [dB] 10 Input level vs. Distortion characteristics 3 (SAP) Input signal: SAP (dbx-TVNR ON) 1kHz, 0dB=100% modulation level VCC=9V, 30kHz using LPF, SAP mode Measurement: L/R out Standard level (100%) -10 0 Input level [dB] 10
10
Distortion (%)
1.0
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CXA1734S
Stereo LPF frequency characteristics 10
5
Gain (dB)
0
-5
-10
0
20
40
60
80
100
Frequency (kHz)
Main LPF and Sub LPF frequency characteristics 30
Gain (FC main and FC sub) (dB)
20 10 0 -10 -20 -30 -40 -50 1 2 5 7 10 20 50 70 100 Frequency (kHz)
SAP frequency characteristics and group delay 100 20 5fH 10 Gain 90 80 70 60 0 50 40 -10
Group delay
30 20
-20 20 40
3.8fH 60 80
6.2fH 100
10 0 120
Frequency (kHz)
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Group delay
Gain (dB)
CXA1734S
Package Outline
Unit : mm
30PIN SDIP (PLASTIC)
+ 0.1 .05 0.25 - 0
+ 0.4 26.9 - 0.1
30
16
+ 0.3 8.5 - 0.1
10.16
0 to 15
1 1.778
15
0.5 0.1 0.9 0.15
PACKAGE STRUCTURE
MOLDING COMPOUND SONY CODE EIAJ CODE JEDEC CODE SDIP-30P-01 SDIP030-P-0400 LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT EPOXY / PHENOL RESIN SOLDER/PALLADIUM PLATING COPPER ALLOY 1.8g
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3.0 MIN
0.5 MIN
+ 0.4 3.7 - 0.1

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